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If anyone's interested, Raymond Chen did a series of posts on the idiosyncranies of the Itanium processor, starting here: [0] [0] https://devblogs.microsoft.co

• thesz 6y ago
  I read it and found that write to R0 (zero read register) triggered CPU fault. This means that there is some hardware that checks condition that will not happen during normal course of events - compiler won't generate such code and write to register that reads zero is harmless. That hardware stays there, occupies space (does not matter how little) and drains energy (no matter how little). This part of hardware is utterly meaningless and shows how priorities were skewed during design phase. It also shows why Itanium was such a bad chip - features were piled up instead of being cut down. RISC-V did cut down on features first (compare division overflow in RISC-V and OpenRISC) and has a process to add them. This is why RISC-V is easy to implement even in OoO variant and why it is being picked up by everyone and their dog.