I'm not sure about the difficulty level of enlarging the pages in Windows. But I'm afraid there are 3rd party programs hardcoding it (and existing ARM hw they r

I'm not sure about the difficulty level of enlarging the pages in Windows. But I'm afraid there are 3rd party programs hardcoding it (and existing ARM hw they run on, etc.) But thinking more about it, IIRC Windows has a 64kB granularity at some level in mapping APIs, so maybe it's not as difficult as I initially thought. Not sure. Why it has an impact on L1? Because you don't want to perform address translation before beginning your L1 lookup (else the perfs would be shit). So you index your L1 cache by the LSb, which are the same in virtual and physical. So a bigger page size means more bits to index, and a bigger L1 without having to give it more ways. And if you can avoid more ways, its better because you have to compare the tags in all the ways, then mux the data out of the good one, so having tons of ways draw some power. That's why L1D is typically 32k on computers with 4kB pages: that gives 8 ways, which is OK. Intel went with 48k and 12 ways on Sunny Cove, but that's starting to be high. A12 is 128k L1D, with 16kB pages, if I'm not mistaken that's conveniently 8 ways.