> While this is certainly true for bleeding edge nodes, hasn't the NRE become significantly lower for mature process chips? I would guess that EDA tools and a g

> While this is certainly true for bleeding edge nodes, hasn't the NRE become significantly lower for mature process chips? I would guess that EDA tools and a greater availability of IP blocks would drive down the real dollar cost of designing your own ASIC on a node 1-2 generations back. Honestly, I'm not familiar enough to have a nuanced opinion, but from what I understand, that's probably true. However, in the battle for cloud VPS and PC CPU sockets, using a 1-2 generation old process doesn't appear to be a winning strategy.