4 ms·Cell with a saner bus/memory access?by protomyth 6y agoCell with a saner bus/memory access?floatboth 6y agoOr Fujitsu A64FX?rbanffy 6y agoIf all cores see a single unified and consistent memory image (some scratchpad memory excepted), it's best if they all share the same basic ISA (and not implemented instructions trap to process migration or software emulation)