So many questions ;-) Yes, I have still quite some fun with FPGAs. I am interested into open source tooling, e.g., using Chisel and want to look into yosys. R

So many questions ;-) Yes, I have still quite some fun with FPGAs. I am interested into open source tooling, e.g., using Chisel and want to look into yosys. Redesign of JOP: 1. switch from VHDL to Chisel, 2. change the cache to be able to read one bytecode per clock cycle, 3. maybe some bytecode fusion (executing more than one per clock cycle), 4. time-predictable branch prediction. Mmh, looks like there is some open work ;-)