3 ms·

Could someone break down the significance of this for those of us who are less hardware-acquainted? Does this represent the cutting edge of RISC-V CPU design? A

by DC-3 6y ago

Could someone break down the significance of this for those of us who are less hardware-acquainted? Does this represent the cutting edge of RISC-V CPU design? And how difficult would it to implement this design properly instead of simply emulating it with an FPGA?

nickik 6y ago
This has been tapped out many times in different ways already. ETH has developed these and given them over for open source management and commercialization. The have a whole host of research projects around low energy cores and different accelerators. The idea is to have very competitive core for the 64bit embedded core that is fully open and has lots of ways to combine it with other cores and other accelerators. This core is cutting edge for a commercial open source embedded 64bit capable chip, but it is not the highest performance core in RISC-V. Play around with this website to see all the ETH chips, many are RISC-V: http://asic.ethz.ch/ http://asic.ethz.ch/
rustybolt 6y ago
Emulation is when a CPU in instruction set A runs machine code in instruction set B. A specification of a piece of hardware called a design and is written in a hardware design language (HDL). The most used HDLs are VHDL (mostly in Europe, I believe) and Verilog (mostly in the USA, I believe). A design is just a set of source files which admit a complete description. To actually implement the design on a physical design, additional steps are needed. Specifically, the code needs to be mapped to the FPGA (this can be divided into a couple of steps: 'translate', 'map', and 'place and route'). This is a messy optimization problem which is typically approached with a stochastic algorithm, and usually takes quite long (think a couple of minutes for trivial designs, and up to 8 hours for complicated designs on big FPGAs). To implement a 'silicon implementation' of a CPU, you also need a layout. I'm not 100% sure how these are done, but I would guess it's some mixture of automatic design, re-use of existing blocks, and manual design by greybeard electrical engineers. The design needs to satisfy some design rules, which are determined by the process that is used. The advantage of having a dedicated layout over having a synthesizable design that you can run on an FPGA, is that it often clocks much faster. I have no idea how much faster though (I think at least 10x?), and I'd guess it depends on the design, process, FPGA, and how good the manual layout is.
- rjsw 6y ago
  > Emulation is when a CPU in instruction set A runs machine code in instruction set B. TBF, the README.md of the repo in the link does have a section on "FPGA Emulation".
Taek 6y ago
A̶s̶ ̶f̶a̶r̶ ̶a̶s̶ ̶I̶'̶m̶ ̶a̶w̶a̶r̶e̶,̶ ̶t̶h̶i̶s̶ ̶i̶s̶ ̶o̶n̶e̶ ̶o̶f̶ ̶t̶h̶e̶ ̶o̶n̶l̶y̶ ̶o̶p̶e̶n̶ ̶s̶o̶u̶r̶c̶e̶ ̶d̶e̶s̶i̶g̶n̶s̶ ̶f̶o̶r̶ ̶a̶ ̶R̶I̶S̶C̶-̶V̶ ̶C̶P̶U̶. While the instruction set of RISC-V itself is unpatented and open source, there's a lot of work that needs to happen between having an instruction set and having a fully designed chip. Hardware development is roughly broken into 2 stages - front end and back end. Front end is where all of the architectural work happens, and is roughly analogous in software to writing the C code for a program. If you can run it on an FPGA, it means the front-end work is basically complete. Back-end work is the equivalent of assembler. Except, instead of compiling to a computer architecture, you are compiling to a "process", such as TSMC 7nm. Every process uses different chemistry and physics to work, so backend work strictly cannot be re-used between processes. The wires and gates etc. have different physical properties and just won't work if you use a backend design on the wrong process. Unlike in programming, the "compilation" process is highly non-trivial. Depending on how much performance optimization you are doing, the back-end work to put this architecture onto say a 7nm process could be tens of millions of dollars. "Compilers" (called place-and-route in hardware) are not very good and need an engineer (or many engineers) babysitting them. And if you want it to go fast, you are going to need to optimize much of it by-hand, which again is highly non trivial. So even though this repo isn't going to get you a completed chip, it's a really great resource if you want to make your own chip, because it gives you an architecture and a full front end implementation. The front-end is where most people consider the "brains" of a project to be, generally a design shop has its best minds working in front end, and many front end engineers look down on backend work as "grunt work". That said, there are plenty of brilliant people on back end as well, and back end is particularly important and difficult if you are doing something like a wifi chip or bluetooth chip.
- tverbeure 6y ago
  There are more open source RISC-V that I can count on two hands. Off the top of my head: Rocket, Boom, Boom II, VexRiscv, Ri5cy, Ariane, Vectorblox, SERV, Swerv EH1, Swerv EH2, picorv32, ...
newhouseb 6y ago
Emulation to me implies simulation, which isn't what an FPGA does. A configured FPGA and an ASIC are both real electric circuits. In an FPGA the building blocks are larger groups of transistors (typically forming "Look Up Tables") that are connected together by a network of a bajillion electronic switches (read: other transistors). In an ASIC the building block is generally a transistor (although technically any structure you can "tape-out" with lithography) and everything is wired up directly. Porting this to an ASIC is more gated by access to proprietary tooling than anything else. There's a number of open source efforts to replicate this tooling on older process nodes (search for SkyWater PDK and OpenROAD). As for how significant this particular RISC-V chip is, there are a bunch of open source RISC-V chips cropping up. This one does seem to have more extensions implemented than the typical RISC-V chip, which is notable. Personally I'm more interested in RISC-V CPUs written in newer tooling (i.e. nMigen or Chisel) rather than Verilog as I find Verilog a trusty but a bit archaic (similar to how C is seen these days).
- monocasa 6y ago
  Emulation just means running it on hardware it wasn't intended. That runs the spectrum between ISA emulators like Dolphin, software RTL simulators like verilator, and FPGAs can certainly be used for emulation if the design wasn't really intended for them as the real end goal. There's also an interesting point in that spectrum of the cadence/synopsys hardware emulators. They run in a rack sized device composed of a bunch of FPGAs and arrays of custom ascetic processor cores that can only do logic and branch ops to run HDL for SoC sized designs at ~1-10MHz.
  - guepe 6y ago
    I know ZeBu very well and... "a bunch of FPGAs" is an understatement. It can go all the way to 1500 FPGAs !

by DC-3 6y ago

nickik 6y ago

This has been tapped out many times in different ways already. ETH has developed these and given them over for open source management and commercialization. The have a whole host of research projects around low energy cores and different accelerators. The idea is to have very competitive core for the 64bit embedded core that is fully open and has lots of ways to combine it with other cores and other accelerators. This core is cutting edge for a commercial open source embedded 64bit capable chip, but it is not the highest performance core in RISC-V. Play around with this website to see all the ETH chips, many are RISC-V: http://asic.ethz.ch/ http://asic.ethz.ch/

rustybolt 6y ago

Emulation is when a CPU in instruction set A runs machine code in instruction set B. A specification of a piece of hardware called a design and is written in a hardware design language (HDL). The most used HDLs are VHDL (mostly in Europe, I believe) and Verilog (mostly in the USA, I believe). A design is just a set of source files which admit a complete description. To actually implement the design on a physical design, additional steps are needed. Specifically, the code needs to be mapped to the FPGA (this can be divided into a couple of steps: 'translate', 'map', and 'place and route'). This is a messy optimization problem which is typically approached with a stochastic algorithm, and usually takes quite long (think a couple of minutes for trivial designs, and up to 8 hours for complicated designs on big FPGAs). To implement a 'silicon implementation' of a CPU, you also need a layout. I'm not 100% sure how these are done, but I would guess it's some mixture of automatic design, re-use of existing blocks, and manual design by greybeard electrical engineers. The design needs to satisfy some design rules, which are determined by the process that is used. The advantage of having a dedicated layout over having a synthesizable design that you can run on an FPGA, is that it often clocks much faster. I have no idea how much faster though (I think at least 10x?), and I'd guess it depends on the design, process, FPGA, and how good the manual layout is.

rjsw 6y ago
> Emulation is when a CPU in instruction set A runs machine code in instruction set B. TBF, the README.md of the repo in the link does have a section on "FPGA Emulation".

Taek 6y ago

A̶s̶ ̶f̶a̶r̶ ̶a̶s̶ ̶I̶'̶m̶ ̶a̶w̶a̶r̶e̶,̶ ̶t̶h̶i̶s̶ ̶i̶s̶ ̶o̶n̶e̶ ̶o̶f̶ ̶t̶h̶e̶ ̶o̶n̶l̶y̶ ̶o̶p̶e̶n̶ ̶s̶o̶u̶r̶c̶e̶ ̶d̶e̶s̶i̶g̶n̶s̶ ̶f̶o̶r̶ ̶a̶ ̶R̶I̶S̶C̶-̶V̶ ̶C̶P̶U̶. While the instruction set of RISC-V itself is unpatented and open source, there's a lot of work that needs to happen between having an instruction set and having a fully designed chip. Hardware development is roughly broken into 2 stages - front end and back end. Front end is where all of the architectural work happens, and is roughly analogous in software to writing the C code for a program. If you can run it on an FPGA, it means the front-end work is basically complete. Back-end work is the equivalent of assembler. Except, instead of compiling to a computer architecture, you are compiling to a "process", such as TSMC 7nm. Every process uses different chemistry and physics to work, so backend work strictly cannot be re-used between processes. The wires and gates etc. have different physical properties and just won't work if you use a backend design on the wrong process. Unlike in programming, the "compilation" process is highly non-trivial. Depending on how much performance optimization you are doing, the back-end work to put this architecture onto say a 7nm process could be tens of millions of dollars. "Compilers" (called place-and-route in hardware) are not very good and need an engineer (or many engineers) babysitting them. And if you want it to go fast, you are going to need to optimize much of it by-hand, which again is highly non trivial. So even though this repo isn't going to get you a completed chip, it's a really great resource if you want to make your own chip, because it gives you an architecture and a full front end implementation. The front-end is where most people consider the "brains" of a project to be, generally a design shop has its best minds working in front end, and many front end engineers look down on backend work as "grunt work". That said, there are plenty of brilliant people on back end as well, and back end is particularly important and difficult if you are doing something like a wifi chip or bluetooth chip.

tverbeure 6y ago
There are more open source RISC-V that I can count on two hands. Off the top of my head: Rocket, Boom, Boom II, VexRiscv, Ri5cy, Ariane, Vectorblox, SERV, Swerv EH1, Swerv EH2, picorv32, ...

newhouseb 6y ago

Emulation to me implies simulation, which isn't what an FPGA does. A configured FPGA and an ASIC are both real electric circuits. In an FPGA the building blocks are larger groups of transistors (typically forming "Look Up Tables") that are connected together by a network of a bajillion electronic switches (read: other transistors). In an ASIC the building block is generally a transistor (although technically any structure you can "tape-out" with lithography) and everything is wired up directly. Porting this to an ASIC is more gated by access to proprietary tooling than anything else. There's a number of open source efforts to replicate this tooling on older process nodes (search for SkyWater PDK and OpenROAD). As for how significant this particular RISC-V chip is, there are a bunch of open source RISC-V chips cropping up. This one does seem to have more extensions implemented than the typical RISC-V chip, which is notable. Personally I'm more interested in RISC-V CPUs written in newer tooling (i.e. nMigen or Chisel) rather than Verilog as I find Verilog a trusty but a bit archaic (similar to how C is seen these days).

monocasa 6y ago
Emulation just means running it on hardware it wasn't intended. That runs the spectrum between ISA emulators like Dolphin, software RTL simulators like verilator, and FPGAs can certainly be used for emulation if the design wasn't really intended for them as the real end goal. There's also an interesting point in that spectrum of the cadence/synopsys hardware emulators. They run in a rack sized device composed of a bunch of FPGAs and arrays of custom ascetic processor cores that can only do logic and branch ops to run HDL for SoC sized designs at ~1-10MHz.
- guepe 6y ago
  I know ZeBu very well and... "a bunch of FPGAs" is an understatement. It can go all the way to 1500 FPGAs !