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Ariane RISC-V CPU – An open source CPU capable of booting Linux
- searedsteak 6y agoLooks like it just shares a name with the spacecraft but isn't related?
- a2800276 6y agoThe European rocket is named after a Cretan princess from Greek mythology. This project is related to the rocket-chip generator. Nerds involved all around :)
- nickik 6y agoThe 'original' RISC-V core was called Rocket. https://github.com/chipsalliance/rocket-chip https://github.com/chipsalliance/rocket-chip So they picked a European rocket as a name.
- Ndymium 6y agoI can't help but think of Ariane V and its famous launch failure due to a programming error. I hope Ariane RISC-V fares better. ;) (Ok, the rocket platform has been reliable since 2003, but that ruins the joke.)
- MaxBarraclough 6y agoWas going to say the same. I learnt of the Ariane 5 explosion in a class on critical-systems software development. The out-of-range error that cost $0.5bn. A summary of the failure: https://www-users.math.umn.edu/~arnold/disasters/ariane.html https://www-users.math.umn.edu/~arnold/disasters/ariane.html
- ncmncm 6y agoIt wasn't even the out-of-range value that caused the failure--that would have been fine. The failure was caused by trapping the error, and dumping debug data onto the realtime control bus.
- Symmetry 6y agoGetting two explosions in the first 20 launches is par for the course in making a new rocket. :)
- j-pb 6y agoI love that the controller symbol is a toilet, because on a miss-predict it does a "flush".
- DC-3 6y agoCould someone break down the significance of this for those of us who are less hardware-acquainted? Does this represent the cutting edge of RISC-V CPU design? And how difficult would it to implement this design properly instead of simply emulating it with an FPGA?
- nickik 6y agoThis has been tapped out many times in different ways already. ETH has developed these and given them over for open source management and commercialization. The have a whole host of research projects around low energy cores and different accelerators. The idea is to have very competitive core for the 64bit embedded core that is fully open and has lots of ways to combine it with other cores and other accelerators. This core is cutting edge for a commercial open source embedded 64bit capable chip, but it is not the highest performance core in RISC-V. Play around with this website to see all the ETH chips, many are RISC-V: http://asic.ethz.ch/ http://asic.ethz.ch/
- rustybolt 6y agoEmulation is when a CPU in instruction set A runs machine code in instruction set B. A specification of a piece of hardware called a design and is written in a hardware design language (HDL). The most used HDLs are VHDL (mostly in Europe, I believe) and Verilog (mostly in the USA, I believe). A design is just a set of source files which admit a complete description. To actually implement the design on a physical design, additional steps are needed. Specifically, the code needs to be mapped to the FPGA (this can be divided into a couple of steps: 'translate', 'map', and 'place and route'). This is a messy optimization problem which is typically approached with a stochastic algorithm, and usually takes quite long (think a couple of minutes for trivial designs, and up to 8 hours for complicated designs on big FPGAs). To implement a 'silicon implementation' of a CPU, you also need a layout. I'm not 100% sure how these are done, but I would guess it's some mixture of automatic design, re-use of existing blocks, and manual design by greybeard electrical engineers. The design needs to satisfy some design rules, which are determined by the process that is used. The advantage of having a dedicated layout over having a synthesizable design that you can run on an FPGA, is that it often clocks much faster. I have no idea how much faster though (I think at least 10x?), and I'd guess it depends on the design, process, FPGA, and how good the manual layout is.
- Symmetry 6y agoCool. No register renaming but scoreboared issue means it's still weakly out of order. It seems to be grabbing the instruction stream in 32 bit chunks but I wonder if it can decode two compressed instructions in a single clock cycle?
- fwsgonzo 6y agoI doubt it because they can cross page-borders which is a seriously annoying "feature" in the compressed extension. Also 32-bit instructions can cross the page border too!
- Symmetry 6y agoThe 32-bit instruction sets I'm familiar with all tend to enforce alignment which means page boundaries aren't a problem. Also, you get 2 extra bits of jump distance for free by not having to specify the exact byte you're jumping too but only the 32 bit word.
- fwsgonzo 6y agoIf you disable the compressed extension then you do get enforced alignment. So, for example RV32I, RV64I both 32-bit alignment. I just ran a small linux program I had for RV32GC and I found 2 places where an instruction crossed a page border. I don't understand why they thought that was a good idea, and for such a modern architecture too, but I guess on hardware it's fine?
- monocasa 6y agoWell, there's a few places were it makes sense and doesn't. And it being an optional extension means that it pretty much exists where it's benefits outweigh it's costs. The really tiny cores with RV-C don't even have page tables, so there's no straddling to worry about. There it's very cheap, and has a lot of benefit, so you see it in the same target (and same reasons) as CortexM cores being Thumb2 based. One level of complexity up, a simple embedded core with a full MMU (taking the place of what'd be a classic 5 stage RISC like in a home router or something) is the least likely to want it, but in those cases you're normally doing buildroot like software anyway, so it's not a big deal that you have to compile everything with rv32g instead of rv32gc. Larger more powerful cores have the gate count necessary to paper over the complexity of straddling page boundaries. And that's why you see the binary distros pretty much requiring RV-C. The increased gate count there is worth the better utilization of the I$.
- ansible 6y agoSo I've had the itch to get a 64-bit RISC-V board of some sort. For reasons I won't get into, I'm not so interested in the 32-bit version. The prices for the Genesys 2 Kintex-7 are $1000 USD at Digikey, which is way too much to spend on a hobby. I suppose I could try to port the FPGA code to a cheaper platform, but I'm no expert on that sort of development. Arguably, I'm not an expert on operating systems development either... On the other end of the spectrum, There is this Canaan Kendryte K210 chip, which is a dual-core 64-bit RISC-V SoC, but only has 8MiBytes of on-chip SRAM, with no provision for SDRAM. An RTOS is of course the straight-forward choice for that, though people are apparently able to run a very slim Linux kernel on it as well. You can get various boards from Seeed Studio for $30 USD or less. Is there something else that is a reasonable price? Less than $100 USD? Yes, I know, qemu is free.
- rjsw 6y agoThere are pre-built images for cheaper FPGA boards. There is one for the Parallella system. A limiting factor on most FPGA dev boards is the amount of RAM if you want to do any software development on the resulting RISC-V SoC.
- jychang 6y agoSeems like a chance to combine it with this: https://news.ycombinator.com/item?id=23755693 https://news.ycombinator.com/item?id=23755693
- Koshkin 6y agoWhat’s so attractive in RISC-V compared to, say, ARM or MIPS? Is it just the license?
- monocasa 6y agoIt's cleaner than ARM or MIPS. AArch32 has something like 1200 instructions these days and a ton of cruft in there. AArch64 has good but not great instruction density, having nothing like ARM Thumb or RV-C. MIPS (or at least what most people mean when they say MIPS) has all sorts of gross stuff like branch delay slots that are a pain in any non 5 stage in order design.
- ncmncm 6y agoRISC-V could be a pretty good ISA, if only it came with a popcount instruction. Given popcount, it is easy to compose a whole range of other essential operations with just one or two more instructions. Without, you are stuck running two dozen instructions just to get to the first step. Is the RISC-V evolutionary process capable of processing small-sized, incremental improvements? Or are only big "extension" instruction families even possible?
- Symmetry 6y agoThe B extension is going to add that. https://github.com/riscv/riscv-bitmanip https://github.com/riscv/riscv-bitmanip Also conditional move which you really need for a lot of reasons but especially to avoid timing attacks in cryptography.
- ncmncm 6y agoThe B extension spec seems to be stagnating. It will anyway be optional and probably rarely implemented even if ever finished. If we have to wait on B, it probably means not getting popcount. Conditional move would be there implicitly if they had defined boolean "true" to be ~0 in the ABI: just AND. Instead they made it 1, so you have to negate it before you can use it for anything. This has been well understood in SIMD circles for decades; it is a mystery how they could have missed it. I am ready for a RISC-VI, RISC-W, or RISD-V "fixed version".
- nickik 6y agoB extension was making good progress after it had slowed down for a while. Seems like standardization has slowed because of COVID. The argument that it will never be implemented seems kind of wrong, why not? Multiple vendors and open source extensions already implemented the essential functionality in non standard ways. In the next standard profile for Linux, the V and B extensions will very likely be included. ISA standardization never happens as fast as you hope it does.
- 6y ago