3 ms·

Maybe we could get Cadence to open source 20 year old software for the 20 year old 130nm chips!

MayeulC 6y ago
I wouldn't count on it: I don't think Cadence internals have changed much since then. And if they were to, I'd say that Cadence itself isn't especially easy to use, nor complicated to replicate. It would feel more like a lock-in attempt. The gEDA project would be a good place to start a new layout-level EDA. It has the necessary tools for simulation, already. Synthesis and place-and-route tools exist, but there are many alternatives, documentation is lacking, and I am not sure that PDK is compatible. I don't know of a good open-source drawing tool, but it shouldn't be too complicated to make a basic one. The more complex part would be to integrate it with DRC (design rule check). An then the usual Layout Schematic Extraction to perform LVS (Layout Versus Schematic) simulation, antenna rules, etc. Thinking about it, it's a good thing that node isn't too advanced. It reduces the design rules complexity by a few orders of magnitude.
- quyleanh 6y ago
  > The more complex part would be to integrate it with DRC (design rule check) If you have open-source design tool (including schematic simulation and verification), I think you will have open-source tool for physical verification. Assume that we still use rule check standard from Mentor Calibre, Assura. > Thinking about it, it's a good thing that node isn't too advanced. It reduces the design rules complexity by a few orders of magnitude. The complexity depends on process. The smaller process, the more complex. There is thousands of rule check even on the old process (180nm, 130nm...).
  - MayeulC 6y ago
    > If you have open-source design tool (including schematic simulation and verification), I think you will have open-source tool for physical verification Right, though the manufacturer will usually automatically run design rules checks on the submitted designs (they don't want you to endanger other people's components due to density or antenna rules). But I was mostly thinking of it being integrated with a manual layout drawing tool: that's a nice-to-have, but not necessary, and more complex for a drawing tool. If you leave that out, creating a drawing tool should be pretty straightforward. > The smaller process, the more complex. Hence my point: it's easier to start with a less-complex process.
- exikyut 6y ago
  >> Maybe we could get Cadence to open source 20 year old software for the 20 year old 130nm chips! "Haha, funny!" > I wouldn't count on it: I don't think Cadence internals have changed much since then. (Sigh)

I wouldn't count on it: I don't think Cadence internals have changed much since then. And if they were to, I'd say that Cadence itself isn't especially easy to use, nor complicated to replicate. It would feel more like a lock-in attempt. The gEDA project would be a good place to start a new layout-level EDA. It has the necessary tools for simulation, already. Synthesis and place-and-route tools exist, but there are many alternatives, documentation is lacking, and I am not sure that PDK is compatible. I don't know of a good open-source drawing tool, but it shouldn't be too complicated to make a basic one. The more complex part would be to integrate it with DRC (design rule check). An then the usual Layout Schematic Extraction to perform LVS (Layout Versus Schematic) simulation, antenna rules, etc. Thinking about it, it's a good thing that node isn't too advanced. It reduces the design rules complexity by a few orders of magnitude.

quyleanh 6y ago
> The more complex part would be to integrate it with DRC (design rule check) If you have open-source design tool (including schematic simulation and verification), I think you will have open-source tool for physical verification. Assume that we still use rule check standard from Mentor Calibre, Assura. > Thinking about it, it's a good thing that node isn't too advanced. It reduces the design rules complexity by a few orders of magnitude. The complexity depends on process. The smaller process, the more complex. There is thousands of rule check even on the old process (180nm, 130nm...).
- MayeulC 6y ago
  > If you have open-source design tool (including schematic simulation and verification), I think you will have open-source tool for physical verification Right, though the manufacturer will usually automatically run design rules checks on the submitted designs (they don't want you to endanger other people's components due to density or antenna rules). But I was mostly thinking of it being integrated with a manual layout drawing tool: that's a nice-to-have, but not necessary, and more complex for a drawing tool. If you leave that out, creating a drawing tool should be pretty straightforward. > The smaller process, the more complex. Hence my point: it's easier to start with a less-complex process.
exikyut 6y ago
>> Maybe we could get Cadence to open source 20 year old software for the 20 year old 130nm chips! "Haha, funny!" > I wouldn't count on it: I don't think Cadence internals have changed much since then. (Sigh)