4 ms·

The Arm Morello Board (2019)

21 points by zxombie 6y ago

justin66 6y ago
Thanks. I've seen this before, but I don't think I noticed this: prototype board to be available from late 2021 I didn't realize the wait would be quite that long.
- zxombie 6y ago
  There will be a simulator later this year. I expect CheriBSD on Morello will released at the same time with a feature set compariable with MIPS and RISC-V.
wyldfire 6y ago
The board seems much less interesting than this feature it delivers. "CHERI" sounds really cool. At first I thought it was a rehash of pointer auth/hw sanitizer ARM features that already exist. But no [1]: > A Portable Architectural Protection Model ... We have experimented with adding the CHERI protection model to a number of ISAs, beginning with 64-bit MIPS, which was the baseline for our original research. More recently, we have developed an experimental version for 64-bit ARMv8-A (in collaboration with Arm), and also for 32/64-bit RISC-V. Something that can work across architectures will see much faster adoption, I'm happy to see it. [1] https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-941.pdf https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-941.pdf
- zxombie 6y ago
  We (University of Cambridge) have added it to MIPS and RISC-V. As the same team did both of these they feel similar. Arm is working closely with us to add it to their architecture, but it has a few differences, mostly to allow for experimentation to see what should be added to the future production architecture.
- waste_monk 6y ago
  Let's hope this Morello CHERI experiment is fruitful.
johnorourke 6y ago
"Show me the way to Arm Morello, tralala la la la la la..."
fanf2 6y ago
If I understand correctly, this is going to be the first custom silicon implementation of a CHERI-style capability architecture. So far the CHERI-MIPS and CHERI-RISC-V implementations have been FPGA-only.
- zxombie 6y ago
  That is correct. We have FPGAs, qemu, and formal models (that can boot an OS) of CHERI-RISC-V and CHERI-MIPS. Most software development uses qemu as it is faster than the FPGAs at around 100MHz. Having something in the GHz range will give us a chance to try things we are currently struggling with, e.g. fuzzing is painfully slow.

21 points by zxombie 6y ago

Thanks. I've seen this before, but I don't think I noticed this: prototype board to be available from late 2021 I didn't realize the wait would be quite that long.

zxombie 6y ago
There will be a simulator later this year. I expect CheriBSD on Morello will released at the same time with a feature set compariable with MIPS and RISC-V.

wyldfire 6y ago

The board seems much less interesting than this feature it delivers. "CHERI" sounds really cool. At first I thought it was a rehash of pointer auth/hw sanitizer ARM features that already exist. But no [1]: > A Portable Architectural Protection Model ... We have experimented with adding the CHERI protection model to a number of ISAs, beginning with 64-bit MIPS, which was the baseline for our original research. More recently, we have developed an experimental version for 64-bit ARMv8-A (in collaboration with Arm), and also for 32/64-bit RISC-V. Something that can work across architectures will see much faster adoption, I'm happy to see it. [1] https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-941.pdf https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-941.pdf

zxombie 6y ago
We (University of Cambridge) have added it to MIPS and RISC-V. As the same team did both of these they feel similar. Arm is working closely with us to add it to their architecture, but it has a few differences, mostly to allow for experimentation to see what should be added to the future production architecture.
waste_monk 6y ago
Let's hope this Morello CHERI experiment is fruitful.

johnorourke 6y ago

"Show me the way to Arm Morello, tralala la la la la la..."

fanf2 6y ago

If I understand correctly, this is going to be the first custom silicon implementation of a CHERI-style capability architecture. So far the CHERI-MIPS and CHERI-RISC-V implementations have been FPGA-only.

zxombie 6y ago
That is correct. We have FPGAs, qemu, and formal models (that can boot an OS) of CHERI-RISC-V and CHERI-MIPS. Most software development uses qemu as it is faster than the FPGAs at around 100MHz. Having something in the GHz range will give us a chance to try things we are currently struggling with, e.g. fuzzing is painfully slow.