I don't think that's the entire reason. Most of the common x86 instructions occurring in a normal program can be decoded to a few uops in a straightforward way,

I don't think that's the entire reason. Most of the common x86 instructions occurring in a normal program can be decoded to a few uops in a straightforward way, and since Sandy Bridge the decoded uops are cached anyway. So this would only be a significant bottleneck for hot loops that are large enough that they don't fit in the uop cache. It's definitely a real issue but it seems wrong to pin all or even most of Intel's stagnation on that.