4 ms·
> but there's also no speedup over an SSE instruction by doing so Just because they are split doesn’t mean they run sequentially. Zen 1 can handle up to 4 floa
by Const-me 6y ago
> but there's also no speedup over an SSE instruction by doing so
Just because they are split doesn’t mean they run sequentially. Zen 1 can handle up to 4 floating point microops/cycle, and there’re 4 floating-point execution units, 128-bit wide / each (that’s excluding load/store, these 4 EUs only compute).
Native 256 bit are even faster due to less micro-ops and potentially more in-flight instructions, but I’m pretty sure even on Zen 1 AVX is faster than SSE.
- innocenat 6y agoIt depends. If EUs are actually the bottleneck then doing SSE or AVX wouldn't have any different in speed in such case. However, when instruction decode/retire is the bottleneck, AVX can be faster. I remembered this can be the case on Intel Sandy Bridge (first-gen AVX, double pumped, retire 3 instructions/cycle), where AVX can sometimes be faster (usually it's not that different) With recent CPUs from both Intel/AMD able to at decode/retire at least 4 instructions per cycle this really cease to be the case.
- Const-me 6y ago> AVX can be faster Yes. Another possible reason for that is instructions without SSE equivalents. I remember working on some software where AVX2 broadcast load instruction helped substantially.