3 ms·
128B is pretty common (especially for outer caches, but even for L1 on some ARM cores), and 32B is not unheard of.
by stephencanon 6y ago
128B is pretty common (especially for outer caches, but even for L1 on some ARM cores), and 32B is not unheard of.
- dragontamer 6y agoI'm fairly certain that DDR4 has 64-byte bursts (64-bit data bus x 8 length bursts per command == 64-bytes per DDR4 operation). I'd expect all modern systems with DDR4 controllers to have 64-byte cache lines or greater. LPDDR4 is a totally different protocol however. Maybe 32-bytes is optimal on cell phones... I don't know much about that.