The shrink is usually done at the fab. I.e. layout designers pretend to draw in a higher nm node, then the fab scales the layout. Like 28->22 nm, or 16->12 nm a

The shrink is usually done at the fab. I.e. layout designers pretend to draw in a higher nm node, then the fab scales the layout. Like 28->22 nm, or 16->12 nm and so on. Transistor models stay roughly the same, often they include SPICE command .option geoshrink=x where x is a desired shrink factor. There may be additional DRC rules for the layout in the lower node that necessitate corrections.