3 ms·

Does anyone have experience with die shrink on modern chips? How does it compare?

• rathel 6y ago
  The shrink is usually done at the fab. I.e. layout designers pretend to draw in a higher nm node, then the fab scales the layout. Like 28->22 nm, or 16->12 nm and so on. Transistor models stay roughly the same, often they include SPICE command .option geoshrink=x where x is a desired shrink factor. There may be additional DRC rules for the layout in the lower node that necessitate corrections.
• monocasa 6y ago
  There's a lot of options with different tradeoffs. I've seen both where they keep most of the mask intact like your 8086 example, and where they just didn't make RTL changes, but still go through the whole tape out process again (normally with what were pretty hands off standard cell designs in the first place). The Zen+ shrink was neat because they only shrunk the individual transistors, but kept their position and spacing the same. So the die was the same size, but just more gaps between gates. I've got a theory the folk who normally sit between RTL and layout were running around with their hair on fire from the Spectre revelations, and didn't have the bandwidth to help with low hanging micro optimizations you'd normally see with a shrink, but only have rumors and speculation to back that up.
  • kristianp 6y ago
    What's the point of doing a shrink, but keeping the die size the same? Power efficiency, using a new fab?
    • monocasa 6y ago
      The choice between better power efficiency, better clock rates, or some combination of the two. Additionally, in the Zen+ case, it was a shrink from TSMC 14nm to TSMC 12nm, which you'd be excused for thinking about as TSMC 14nm+++++. Not a lot of design rules changed.