5 ms·
I'm saying that everyone making CPUs uses a strongly ordered cache coherency subsystem and re-ordering only comes from "pipeline effects" [1]. Slightly longer
by BeeOnRope 6y ago
I'm saying that everyone making CPUs uses a strongly ordered cache coherency subsystem and re-ordering only comes from "pipeline effects" [1].
Slightly longer version of the same claim here:
https://news.ycombinator.com/item?id=23661588 https://news.ycombinator.com/item?id=23661588
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[1] I prefer the term core-local because I think it's somewhat more accurate as it can include things like the delayed processing of invalidations and sibling core interactions in SMT which might not fall under "pipeline" effects but are still local to the (physical) core.
- ajross 6y agoThat may well be true in ARM application processors, at least between CPUs. Though nothing in the architectural memory model guarantees that so I'd be surprised if there weren't some surprises (DMA on most of those CPUs is upstream of the cache, for example, and not susceptible to that kind of optimization). I can guarantee it's not for "everyone making CPUs". I'm literally writing code as we speak on a multi CPU cache-incoherent system. It's a big world.
- jeffreygoesto 6y agoTriCore by any chance? ;-)
- ajross 6y agoXtensa