Provided that the software is correctly written, ARM's weaker memory model allows for more flexible instruction and I/O scheduling. It seems most people feel t

Provided that the software is correctly written, ARM's weaker memory model allows for more flexible instruction and I/O scheduling. It seems most people feel that the DEC Alpha went too far in weakening the memory model to improve performance, but A64 seems to at least be near the sweet spot. It's also not a huge amount of work that gets thrown away decoding x86 instructions in parallel, but there's non-zero overhead introduced by having the start location of the next instruction depend on what the current instruction is.