3 ms·
Wow. I know very little about FPGAs and hardware and this is pure magic to me. Debugging these things must be a royal pain.
by jtchang 6y ago
Wow. I know very little about FPGAs and hardware and this is pure magic to me. Debugging these things must be a royal pain.
- pjc50 6y agoYes, it is :) The normal development flow for FPGA software is similar to ASIC in that people focus on testing as many elements as possible in software simulation to a very high level of coverage before even downloading to the FPGA. Once in there, you're reliant on JTAG (high-speed serial bus) to read out values from the target device. Tools like ChipScope can let you see what's going on and set ""breakpoints"". http://web.mit.edu/6.111/www/labkit/chipscope.shtml http://web.mit.edu/6.111/www/labkit/chipscope.shtml All of this is much harder when it's on a board you didn't design!