No. First of all, the efficiency is part of the binning process (some chips are just worse than others). But adding the logic to be able to scale to that many d

No. First of all, the efficiency is part of the binning process (some chips are just worse than others). But adding the logic to be able to scale to that many die (high speed SERDES, large caches with lots of cache coherency traffic flying around) takes up more power, and doing the engineering for a large interposer where one wasn't needed before, enlarging the package the interposer sits in, etc. is expensive. Gluing together a lot of defective die on an expensive interposer/package is a bad idea from just about every perspective.