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Sorry meant A64 rather than aarch64 as pretty sure that Apple hasn't supported 32 bit for a while now (so no T32 or Thumb) so the instruction set was announced
by klelatti 6y ago
Sorry meant A64 rather than aarch64 as pretty sure that Apple hasn't supported 32 bit for a while now (so no T32 or Thumb) so the instruction set was announced in 2010 and definitely cleaner than x86.
Agreed that CISC vs RISC is very questionable by now.
- KMag 6y agoProvided that the software is correctly written, ARM's weaker memory model allows for more flexible instruction and I/O scheduling. It seems most people feel that the DEC Alpha went too far in weakening the memory model to improve performance, but A64 seems to at least be near the sweet spot. It's also not a huge amount of work that gets thrown away decoding x86 instructions in parallel, but there's non-zero overhead introduced by having the start location of the next instruction depend on what the current instruction is.
- saagarjha 6y agoThe weaker memory model also uncovers synchronization bugs that have been papered over by x86's stronger semantics ;)