4 ms·
SVE is whatever width the chip designer wants, Fujitsu's implementation is 512-bit according to AnandTech
by floatboth 6y ago
SVE is whatever width the chip designer wants, Fujitsu's implementation is 512-bit according to AnandTech
- gnufx 6y agoI know, but it's different apart from coming in different hardware widths, as ARM techies will gush.
- jabl 6y agoYes, SVE, like the RISC-V vector extension, is a "real" vector ISA, with things like vector length register (no need for a scalar loop epilog), scatter/gather memory ops for sparse matrix work, mask registers for if-conversion, looser alignment requirements (no/less need for loop prologues). That being said, apart from becoming wider, AVX-NNN has also gotten more "real" vector features with every generation. The difference might not be as huge anymore.