3 ms·
That's pretty cool! That probably means that applications will have an easier time. Looks like it has 512-bit SIMD. I wonder what BLAS they are using, and if t
by ViralBShah 6y ago
That's pretty cool! That probably means that applications will have an easier time. Looks like it has 512-bit SIMD.
I wonder what BLAS they are using, and if the contributions are open sourced.
- gnufx 6y ago(SVE isn't 512-bit SIMD like AVX512.) I don't know what BLAS they're using, though I know they've long worked on their own, but BLIS has gained SVE support recently, for what it's worth.
- floatboth 6y agoSVE is whatever width the chip designer wants, Fujitsu's implementation is 512-bit according to AnandTech
- gnufx 6y agoI know, but it's different apart from coming in different hardware widths, as ARM techies will gush.
- jabl 6y agoYes, SVE, like the RISC-V vector extension, is a "real" vector ISA, with things like vector length register (no need for a scalar loop epilog), scatter/gather memory ops for sparse matrix work, mask registers for if-conversion, looser alignment requirements (no/less need for loop prologues). That being said, apart from becoming wider, AVX-NNN has also gotten more "real" vector features with every generation. The difference might not be as huge anymore.