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Given that today's HPC architectures are mostly power constrained, and a majority of the FLOPS often come from GPUs (for their flop/watt ratios), this direction
by ViralBShah 6y ago
Given that today's HPC architectures are mostly power constrained, and a majority of the FLOPS often come from GPUs (for their flop/watt ratios), this direction is not surprising.
ARM has been making major strides in the high performance area. The new AWS Graviton processors are pretty nice from what I have heard. And then there's the ARM in Mac. Yup and Julia will run on all of these!
While I say all of this, I should also point out that the top500 benchmark pretty much is not representative of most real-life workloads, and is largely based on your ability to solve the largest dense linear solve you possibly can - something almost no real application does.
(The website is down, so I haven't been able to look at the specs of the actual machine).
- fhqghds 6y agoGet ready for a surprise then: all those FLOPS are coming from the ARM cores.... This beast has no GPUs: https://postk-web.r-ccs.riken.jp/spec.html https://postk-web.r-ccs.riken.jp/spec.html
- ViralBShah 6y agoThat's pretty cool! That probably means that applications will have an easier time. Looks like it has 512-bit SIMD. I wonder what BLAS they are using, and if the contributions are open sourced.
- gnufx 6y ago(SVE isn't 512-bit SIMD like AVX512.) I don't know what BLAS they're using, though I know they've long worked on their own, but BLIS has gained SVE support recently, for what it's worth.
- floatboth 6y agoSVE is whatever width the chip designer wants, Fujitsu's implementation is 512-bit according to AnandTech
- gnufx 6y agoI know, but it's different apart from coming in different hardware widths, as ARM techies will gush.
- jabl 6y agoYes, SVE, like the RISC-V vector extension, is a "real" vector ISA, with things like vector length register (no need for a scalar loop epilog), scatter/gather memory ops for sparse matrix work, mask registers for if-conversion, looser alignment requirements (no/less need for loop prologues). That being said, apart from becoming wider, AVX-NNN has also gotten more "real" vector features with every generation. The difference might not be as huge anymore.
- leeter 6y agoSo looking at anandtech's breakdown the CPUs are closer to a knights landing 'CPU/GPU' than a traditional CPU (currently). They also have a ton of HBM2 right next to the dies so this should be insanely fast as they can feed those cores very very quickly regardless of how fast each core is by clock and pipeline. That should massively reduce stalls.
- stephencanon 6y agoThe "traditional CPU" portion of the core is a bit more capable than KNL, but yeah, that's roughly accurate.
- leeter 6y agoOh agreed, but honestly what makes this so interesting is how tuned it is. I'm honestly surprised we haven't seen Intel or AMD ship an HPC CPU with on package HBM2 yet.
- gnufx 6y agoAs an early user of KNL, I don't get the "GPU" bit. KNL runs normal x86_64 code and doesn't look that much different to the AMD Interlagos systems I once used apart from the memory architecture.
- leeter 6y agoIt comes from the fact that KNL came from Larrabee which was actually developed as a GPU initially (and even ran games... sort of) but was never actually released. The next revision of that was the Xeon Phi chips you used. So the connection is "Lots of small cores with lots of high bandwidth ram" although these cores are definitely superscalar where Larrabee and derivatives were not really. https://en.wikipedia.org/wiki/Xeon_Phi https://en.wikipedia.org/wiki/Xeon_Phi https://en.wikipedia.org/wiki/Larrabee_(microarchitecture) https://en.wikipedia.org/wiki/Larrabee_(microarchitecture)
- gnufx 6y ago
- Merrill 6y agoIt looks like this is not an ARM core, but a Fujitsu implementation of the Arm v8-A instruction set and Fujitsu-developed Scaleable Vector Extension. Most likely the latter is doing all the heavy lifting. https://www.fujitsu.com/global/about/resources/news/press-releases/2018/0822-02.html https://www.fujitsu.com/global/about/resources/news/press-re... >A64FX is the world's first CPU to adopt the Scalable Vector Extension (SVE), an extension of Armv8-A instruction set architecture for supercomputers. Building on over 60 years' worth of Fujitsu-developed microarchitecture, this chip offers peak performance of over 2.7 TFLOPS, demonstrating superior HPC and AI performance.
- d_tr 6y agoThe text you linked to actually says that the SVE was developed cooperatively by Fujitsu and ARM, without, however, going into details about who did what.
- numpad0 6y agoThere are words floating that A64fx is basically a SPARC with ARM ISA without much ARM IP in it, no idea how accurate but intriguing
- d_tr 6y agoI am really happy to have come across this post, mainly due to this fact.
- stephencanon 6y agoWorth noting that Fugaku has no GPU/accelerator; all the compute is located in-core (cpu). The core itself has some GPU-like qualities, of course, since it's more optimized for semi-uniform compute throughput than a "normal" CPU is.
- wenc 6y ago> based on your ability to solve the largest dense linear solve you possibly can - something almost no real application does. Sounds right. I was going to say what about large-scale optimization problems? But I realized that most typically only require sparse linear solves. Gradient descent does require the solution of dense Ax=b systems. But the most visible/popular application of large-scale gradient descent today, neural networks, typically use SGD which require no dense linear solves at all.
- gpderetta 6y agoFujitsu has been building its own HPC CPUs, for a long time, whether they use the ARM architecture or SPARC doesn't probably matter much for them. They know how to make them fast.
- bashinator 6y agoYup, one of my first jobs out of college was at HAL.
- tasogare 6y ago> And then there's the ARM in Mac. Are you posting from the future or referring to the T2 chips?
- kohtatsu 6y agoIt was officially announced at the end of the WWDC event today.
- Symmetry 6y agoI'll count myself as someone surprised, given that GPUs are often better tuned to HPC code, that Fujitsu was able to do so well with an Intel Phi approach of just using larger vector units on general purpose CPUs. I wouldn't have thought you could make an out of order core efficiently support scatter/gather the way this thing seems to, though I guess it's possible that the vector unit is in order. Well, the proof is in the pudding and hats off to Fujitsu and ARM.
- calaphos 6y ago> While I say all of this, I should also point out that the top500 benchmark pretty much is not representative of most real-life workloads, and is largely based on your ability to solve the largest dense linear solve you possibly can - something almost no real application does. They also publish the HPCG benchmark with sparse matrixes. And unsurprisingly an order of magnitude lower flops across the board. The Fujitsu chip scales a whole lot better than the usual Nvidia GPUs though.