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The just announced Intel Xeon Cooper Lake top end processor has about 38.5MB of cache. The AMD Rome top end has 256MB of cache. https://ark.intel.com/content/w

The just announced Intel Xeon Cooper Lake top end processor has about 38.5MB of cache. The AMD Rome top end has 256MB of cache. https://ark.intel.com/content/www/us/en/ark/products/205684/intel-xeon-platinum-8380hl-processor-38-5m-cache-2-90-ghz.html https://ark.intel.com/content/www/us/en/ark/products/205684/... https://www.amd.com/en/products/cpu/amd-epyc-7h12 https://www.amd.com/en/products/cpu/amd-epyc-7h12

lend000 6y ago
Interesting, that's news to me. Guess Intel just has clock speed then. That's why I still pay a premium to run certain jobs on z1d or c5 instances. As another commenter pointed out, though, not all caches are equal. Unfortunately, I was not able to easily find access speeds for specific processors, so single-threaded benchmarks are the primary quantitative differentiator.
rckoepke 6y ago
I'm not sure this is the whole story, Intel has twice the L2 cache as AMD but I'm not sure that's enough to make a huge difference. Epyc 7H12[1]: - L1: two 32KiB L1 cache per core - L2: 512KiB L2 cache per core - L3: 16MiB L3 cache per core, but shared across all cores. The L1/L2 cache aren't yet publicly available for any Cooper Lake processors, however the previous Cascade Lake architecture provided: All Xeon Cascade Lakes[2]: - L1: two 32 KiB L1 cache per core - L2: 1 MiB L2 cache per core - L3: 1.375 MiB L3 cache per core (shared across all cores) Normally I'd expect the upcoming Cooper Lake to surpass AMD in L1, and lead further in L2 cache. However it looks like they're keeping the 1.375MiB L3 cache per core in Cooper Lake, so maybe L1/L2 are also unchanged. 0: https://www.hardwaretimes.com/cpu-cache-difference-between-l1-l2-and-l3-cache-explained-and-a-look-at-memory-mapping/ https://www.hardwaretimes.com/cpu-cache-difference-between-l... 1: https://en.wikichip.org/wiki/amd/epyc/7h12 https://en.wikichip.org/wiki/amd/epyc/7h12 2: https://en.wikichip.org/wiki/intel/xeon_platinum/9282 https://en.wikichip.org/wiki/intel/xeon_platinum/9282 Edit: Previously I showed EPYC having twice the L1 as Cascade Lake, this was a typo on my part, they're the same L1 per core.
- deagle50 6y ago
  Zen 2 has 4MiB L3 per core, 16 MiB shared in one 4-core CCX.
  - rckoepke 6y ago
    Thanks, I wrote that while burning the midnight oil and didn't double-check the sanity of those numbers. It's too late to edit mine but I hugely appreciate the clarification.
    - deagle50 6y ago
      NP. It's still a huge amount of LLC compared to the status quo. Says something about how expensive it really is to ship all that data between the CCXs/CCDs.
AdrianB1 6y ago
Cache per tier matters a lot, total cache does not tell much. L1 is always per core and small, L2 is larger and slower, L3 is shared across many cores and access is really slow compared to L1 and L2. In the end performance per watt for a specific app is what matters, that is the end goal.
ju-st 6y ago
Intel L3 does not equal AMD L3 cache regarding latencies. Depending on the application this can matter a lot. https://pics.computerbase.de/7/9/1/0/2/13-1080.348625475.png https://pics.computerbase.de/7/9/1/0/2/13-1080.348625475.png
- kllrnohj 6y ago
  You'd need that latency to be significant enough that AMD's >2x core count doesn't still result in it winning by a landslide anyway, and you need L3 usage low enough that it still fits in Intel's relatively tiny L3 size. There's been very few cloud benchmarks where 1P Epyc Rome hasn't beaten any offering from Intel, including 2P configurations. The L3 cache latency hasn't been a significant enough difference to make up the raw CPU count difference, and where L3 does matter the massive amount of it in Rome tends to still be more significant. Which is kinda why Intel is just desperately pointing at a latency measurement slide instead of an application benchmark.

lend000 6y ago

Interesting, that's news to me. Guess Intel just has clock speed then. That's why I still pay a premium to run certain jobs on z1d or c5 instances. As another commenter pointed out, though, not all caches are equal. Unfortunately, I was not able to easily find access speeds for specific processors, so single-threaded benchmarks are the primary quantitative differentiator.

rckoepke 6y ago

I'm not sure this is the whole story, Intel has twice the L2 cache as AMD but I'm not sure that's enough to make a huge difference. Epyc 7H12[1]: - L1: two 32KiB L1 cache per core - L2: 512KiB L2 cache per core - L3: 16MiB L3 cache per core, but shared across all cores. The L1/L2 cache aren't yet publicly available for any Cooper Lake processors, however the previous Cascade Lake architecture provided: All Xeon Cascade Lakes[2]: - L1: two 32 KiB L1 cache per core - L2: 1 MiB L2 cache per core - L3: 1.375 MiB L3 cache per core (shared across all cores) Normally I'd expect the upcoming Cooper Lake to surpass AMD in L1, and lead further in L2 cache. However it looks like they're keeping the 1.375MiB L3 cache per core in Cooper Lake, so maybe L1/L2 are also unchanged. 0: https://www.hardwaretimes.com/cpu-cache-difference-between-l1-l2-and-l3-cache-explained-and-a-look-at-memory-mapping/ https://www.hardwaretimes.com/cpu-cache-difference-between-l... 1: https://en.wikichip.org/wiki/amd/epyc/7h12 https://en.wikichip.org/wiki/amd/epyc/7h12 2: https://en.wikichip.org/wiki/intel/xeon_platinum/9282 https://en.wikichip.org/wiki/intel/xeon_platinum/9282 Edit: Previously I showed EPYC having twice the L1 as Cascade Lake, this was a typo on my part, they're the same L1 per core.

deagle50 6y ago
Zen 2 has 4MiB L3 per core, 16 MiB shared in one 4-core CCX.
- rckoepke 6y ago
  Thanks, I wrote that while burning the midnight oil and didn't double-check the sanity of those numbers. It's too late to edit mine but I hugely appreciate the clarification.
  - deagle50 6y ago
    NP. It's still a huge amount of LLC compared to the status quo. Says something about how expensive it really is to ship all that data between the CCXs/CCDs.

AdrianB1 6y ago

Cache per tier matters a lot, total cache does not tell much. L1 is always per core and small, L2 is larger and slower, L3 is shared across many cores and access is really slow compared to L1 and L2. In the end performance per watt for a specific app is what matters, that is the end goal.

ju-st 6y ago

Intel L3 does not equal AMD L3 cache regarding latencies. Depending on the application this can matter a lot. https://pics.computerbase.de/7/9/1/0/2/13-1080.348625475.png https://pics.computerbase.de/7/9/1/0/2/13-1080.348625475.png

kllrnohj 6y ago
You'd need that latency to be significant enough that AMD's >2x core count doesn't still result in it winning by a landslide anyway, and you need L3 usage low enough that it still fits in Intel's relatively tiny L3 size. There's been very few cloud benchmarks where 1P Epyc Rome hasn't beaten any offering from Intel, including 2P configurations. The L3 cache latency hasn't been a significant enough difference to make up the raw CPU count difference, and where L3 does matter the massive amount of it in Rome tends to still be more significant. Which is kinda why Intel is just desperately pointing at a latency measurement slide instead of an application benchmark.