5 ms·
The thing that puzzles me is there are 6 values for TYP (patent col 24 line 63) but only two bits instead of three. So they must be doing something tricky like
by kens 6y ago
The thing that puzzles me is there are 6 values for TYP (patent col 24 line 63) but only two bits instead of three. So they must be doing something tricky like borrowing a bit from A or B.
Also, kiwidrew, if you're examining this closely, the 2 bits go from CR INC to the MUX, not to CR INC. What they are doing is generating a microcode start address from the instruction, and assigning 16 micro-instructions to that instruction by default. CR INC is a counter that steps through these micro-instructions. The idea is that most instruction (< 16 micro-instructions) won't need to do any jumps. A tricky part is that 2 bits of CR INC are part of the microcode row address, while the other 2 bits select 1/4 of the row. In other words, there are four 21-bit micro-instructions in each physical 84-bit row, so the ROM array isn't excessively tall and skinny.
- kiwidrew 6y agoAh ha, thanks for explaining CR INC, that makes sense now. I have only been looking at the diagrams in the patent. The patent does enumerate (col 25 line 15) the TYP values: 0, 1, 4, 5, and 6. (The microcode listings also sometimes use a value of 7 for TYP.) So this would suggest that types 0 [conditional jump] and 1 [ALU operation] use a full 5-bit A field (to set the ALU opcode) while types 4-7 use a different format for the A and B fields. The MSB of TYP would select between the two formats, and this would explain the absence of a type 2 or type 3 instruction.