Zen 2 isn't a dual ported singular 32mb L3, its two distinct 16mb L3s. If you need data from one, but your core is from the other, you have to pay the cost. Du

Zen 2 isn't a dual ported singular 32mb L3, its two distinct 16mb L3s. If you need data from one, but your core is from the other, you have to pay the cost. Due to Zen 2 monolithic IO dies make this cost far smaller than the Zen/Zen+ design, since it only has to route inside of the IO die, and not use valuable IF<->chiplet lanes. AMD has soft confirmed that they are rolling with 8 core CCXs, so for desktop Ryzens that are 8 cores or less, it will be a single CCD with a single CCX inside, thus a single L3 domain. And yes, you are correct: if they turn it into a single, but dual ported, L3, two CCXes in a CCD would also be fine and optimal. However, this seems to be more complex than just making bigger CCXes. Intel has horrifically overcomplex memory controller designs because this is how they typically design things, and AMD wants to avoid repeating that mistake.