3 ms·
> Although, honestly, unless you need a computer today, and as much as I love Zen 2, wait for Zen 3 as long as you can. Zen 3 uses 8 core CCXes, which eliminate
by d1zzy 6y ago
> Although, honestly, unless you need a computer today, and as much as I love Zen 2, wait for Zen 3 as long as you can. Zen 3 uses 8 core CCXes, which eliminates the semi-NUMA split L3 latency issue.
Not sure about this. Today in Zen 2, in a 4 core CCX the L3 cache is split between the 4 cores and a core can only directly access its own slice of it and has to go through the Infinity Fabric to access L3 cache of other cores in the same CCX. Just because Zen 3 has 8 cores CCX doesn't necessarily mean that they all access the entire CCX L3 in uniform manner. The latter seems much more important to me than bundling 8 cores in a CCX.
Do you have any links that support that statement that cores inside a CCX will have uniform L3 access in Zen 3? I can only find rumors, no official information on this.
- DiabloD3 6y agoZen 2 isn't a dual ported singular 32mb L3, its two distinct 16mb L3s. If you need data from one, but your core is from the other, you have to pay the cost. Due to Zen 2 monolithic IO dies make this cost far smaller than the Zen/Zen+ design, since it only has to route inside of the IO die, and not use valuable IF<->chiplet lanes. AMD has soft confirmed that they are rolling with 8 core CCXs, so for desktop Ryzens that are 8 cores or less, it will be a single CCD with a single CCX inside, thus a single L3 domain. And yes, you are correct: if they turn it into a single, but dual ported, L3, two CCXes in a CCD would also be fine and optimal. However, this seems to be more complex than just making bigger CCXes. Intel has horrifically overcomplex memory controller designs because this is how they typically design things, and AMD wants to avoid repeating that mistake.