ARMs have a more relaxed memory model than x86 so that would be a complication, though I suppose you could just have the decoder put barriers everywhere. x86 i

ARMs have a more relaxed memory model than x86 so that would be a complication, though I suppose you could just have the decoder put barriers everywhere. x86 is infamously hard to decode, though. Often you speed it up by tagging instruction boundaries in the L1$ which you wouldn't have in the Apple ARM devices by default. If you're willing to just decode one x86 instruction per cycle I suppose the overhead wouldn't be unreasonable.