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RISC cpus have historically been under-clocked and perceivable slower than their cisc competitors. Apple was running on risc cpus before going intel x86. They w
by ianai 6y ago
RISC cpus have historically been under-clocked and perceivable slower than their cisc competitors. Apple was running on risc cpus before going intel x86. They were constantly marketing their speeds as less important than speeds matter to x86 architecture.
I hope they’re able to devote two cores to UI/UX at a much higher frequency than the general compute cores. That would take some engineering know how, but could negate the performance complaints largely.
- Symmetry 6y agoThat's just a matter of the process node Apple's PowerPC chips were on. When RISC chips came out their big selling point was that they could be clocked many times faster than CISC chips at the time could because it was easier to pipeline them and because you could put the entire CPU on a single chip.
- kmeisthax 6y ago"RISC" isn't a single architecture, it's a philosophy for designing architectures. The "RISC" Apple was using before x86 was called PowerPC, and it was designed mostly by IBM. It was also a horrible piece of overheating garbage that I'm still honestly surprised wound up in the Xbox 360 and PlayStation 3. The "RISC" Apple is using now, ARM, is a far more practical architecture that Apple has already beat Intel with in single-thread perf... at a lower clock rate, with strict power limits. Letting the A13 stretch it's legs with wall power and a big heatsink would completely crush Intel and x86 in every benchmark except multi-threading. User-perceived latency has little to do with the clock rate of a processor, though. What you need is: 1. Immediate feedback upon user input 2. Progress animations that move, even if progress is indeterminate 3. High frame rates on your animations 4. No frame stutter or torn frames Out of the four, low clock rate will mainly impact frame rates and pacing, but that can still be mitigated by using what you have as efficiently as possible.