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> An open source set of EDA tools is actually the last roadblock. This is not true. As of last year it is possible to design a complete chip with open source E

> An open source set of EDA tools is actually the last roadblock. This is not true. As of last year it is possible to design a complete chip with open source EDA tools and has been demonstrated on RISC-V with the Raven platform [1]. Though this was previously true. There is debate amongst the community if open foundry tools are essential - with rms surprisingly coming down on the side of “no” with many caveats - but to date there has not been a single chip made with an open source design flow and an open source process technology because while previously there were open source EDA tools there previously were not open source PDK’s. Now there are. Hence the watershed moment. [1] https://youtu.be/r3GLdsSXcxY https://youtu.be/r3GLdsSXcxY

bsder 6y ago
That design used X-FAB proprietary digital standard cells, I/O cells, analog IP, and SRAM. Basically, they used XFAB to do the detailed design and extraction of the blocks. And then they assembled the blocks via place and route. They also didn't push the technology very hard so they could get away with simple static timing analysis. 100MHz in 180nm for a really simple RISC is ridiculously slow--PowerPC chips were 100MHz+ in 500nm. You will note that for EMIR drop--nothing. For signal integrity--nothing. Extraction and DRC is Magic--that's ... laughable is being nice. Don't get me wrong, this is a great achievement. Pulling all these pieces together is really difficult. However, we have been able to do this much for almost a decade+ now. I remember a different European initiative that did similar projects. The difference was that it tried to go after the analog blocks, as well. It failed for lack of accurate extraction. The whole movement flounders on DRC and extraction. Without those, you cannot do the detailed design and analysis to build the fundamental blocks that you need to make interesting chips.

bsder 6y ago

That design used X-FAB proprietary digital standard cells, I/O cells, analog IP, and SRAM. Basically, they used XFAB to do the detailed design and extraction of the blocks. And then they assembled the blocks via place and route. They also didn't push the technology very hard so they could get away with simple static timing analysis. 100MHz in 180nm for a really simple RISC is ridiculously slow--PowerPC chips were 100MHz+ in 500nm. You will note that for EMIR drop--nothing. For signal integrity--nothing. Extraction and DRC is Magic--that's ... laughable is being nice. Don't get me wrong, this is a great achievement. Pulling all these pieces together is really difficult. However, we have been able to do this much for almost a decade+ now. I remember a different European initiative that did similar projects. The difference was that it tried to go after the analog blocks, as well. It failed for lack of accurate extraction. The whole movement flounders on DRC and extraction. Without those, you cannot do the detailed design and analysis to build the fundamental blocks that you need to make interesting chips.