"Not enough space on the die" is so obviously literally wrong that the Intel source obviously didn't mean it literally. "Space on the die" is a global constrain

"Not enough space on the die" is so obviously literally wrong that the Intel source obviously didn't mean it literally. "Space on the die" is a global constraint, but hw design is full of local constraints. Eg, if there are enough pieces of logic and wiring that are connected closely together , then in that area of the die there may not be enough room to fit any more logic or wiring, even though it may occupy a trivial amount of space in terms of the whole die - without violating the gate delay targets that keep the chip running at the correct speed. That's what I'd guess as the meaning, anyway.