4 ms·

Transistor count is the wrong metric because we've been increasing die area as well as shrinking process nodes... It's not sustainable to keep increasing die ar

by tomxor 6y ago

Transistor count is the wrong metric because we've been increasing die area as well as shrinking process nodes... It's not sustainable to keep increasing die areas, so it's not a pivot for moores law.

CyberDildonics 6y ago
Moore's law is about transistor count. Not only that but you are saying the exact opposite in reply to someone else, claiming that process node sizes don't matter.
- tomxor 6y ago
  Moores law is about the rate of transistor count AND the implications. If you read Moore's paper you will find the context in which the definition resides is based on transistor scale, and the implication was even explicitly expressed in the very same paper by Moore - He observed that transistor doubling by reduced transistor scale gave faster clock at the same power density for the same die area. This is no longer true, we are barely still reducing transistor scale (but no longer uniformly), and no longer gain any of the other benefits due to the break down of Dennard scaling, coincidentally at the same time it became difficult to continue to reduce transistor channel scale.
  - CyberDildonics 6y ago
    > rate of transistor count That doesn't really make sense. It was actually about transistor count and cost. > faster clock at the same power density That's Dennard scaling as someone already mentioned to you You said: > Transistor scaling (dennard scaling) Those are two different things. You also said: > We haven't been making significant progress over the last decade in terms of process size, This is false by any reasonable definition, since as has already been said by multiple people, transistors are a fraction of the size they were ten years ago and the density has gone up considerably. > coincidentally at the same time it became difficult to continue to reduce transistor channel scale. Frequencies did not go up, but transistors shrunk, I'm not sure why you keep trying to state otherwise. How do you explain the enormous rise in transistor count and process shrinkage over the last decade? You are literally stating something that is false and not even backing up what you are saying with any information at all.
    - tomxor 6y ago
      I've no wish to be so adversarial with you, but there are clearly some misunderstandings between us so I'll try to answer your questions. but then I'm done. As I have already admitted in the sibling thread, it is not as simple as transistor scaling stopping outright, I was clearly _wrong_ to suggest that... but it's also untrue to suggest transistor scaling has not stopped in any way - this is essentially the point I am still trying to make for you: Features are getting stuck due to various fundamental limits, and we no longer get the same benefits as a result, and this all started at the same time we stopped getting significant speed improvements (the breakdown of Dennard scaling). >> rate of transistor count > That doesn't really make sense. It was actually about transistor count and cost. Yes, but that is a bi-product, It is fundamentally about the exponential growth rate of transistor count per unit area which is only achieved sustainably (until fundamental limits) via transistor scaling. When that scaling is uniform we get not only reduced cost per transistor and but higher speeds: > Moore's law is the observation that the number of transistors in a dense integrated circuit (IC) doubles about every two years. [0] -- >> faster clock at the same power density > That's Dennard scaling as someone already mentioned to you Dennard scaling is a formalization of what Moore already observed in the very same paper a decade prior on page 3 under "Heat problem": > shrinking dimensions on an inte-grated structure makes it possible to operate the structure at higher speed for the same power per unit area. [1] This is the context of Moore's law, the only mechanism at the time that he was alluding to, uniform transistor scaling with all the benefits (including what is known as Dennard scaling today). This context is commonly lost by people who quote it today. -- > You said: >> Transistor scaling (dennard scaling) > Those are two different things. Yes they are, as I already admitted in the sibling subthread, I was technically incorrect to mix them, never the less they are closely related - Dennard scaling has always been related to transistor scale, and broke down at the same time uniform transistor scaling aka "classic transistor scaling" stopped. -- > You also said: >> We haven't been making significant progress over the last decade in terms of process size, > This is false by any reasonable definition, since as has already been said by multiple people, transistors are a fraction of the size they were ten years ago and the density has gone up considerably. I've already admitted this is inaccurate in the sibling thread. You can read my response there. However progress has been stifled to say the least. -- >> coincidentally at the same time it became difficult to continue to reduce transistor channel scale. > Frequencies did not go up, but transistors shrunk, I'm not sure why you keep trying to state otherwise. How do you explain the enormous rise in transistor count and process shrinkage over the last decade? You are literally stating something that is false and not even backing up what you are saying with any information at all. I am not disputing transistors have shrunk, but not all features of transistors have shrunk at the same rate, I'll add emphasis: channel lengths have become more difficult to reduce in scale. Here's a random source I found: > when we approach the direct source-drain tunneling limit, we could move to recessed channel devices and use channel lengths longer than the minimum feature size. This could allow us to continue miniaturization and increase component density. [2] i.e channel lengths will _not_ be 5nm Densities continue to increase while transistors can no longer be uniformly shrunk, in the same way a square can be made into a rectangle and have a smaller area while not reducing the maximum edge length. However it's intuitive to see that while this will continue to increase density, it will not necessarily increase speed - and it will not be long until we hit limits on scaling the other features. [0] https://en.wikipedia.org/wiki/Moore%27s_law https://en.wikipedia.org/wiki/Moore%27s_law [1] https://newsroom.intel.com/wp-content/uploads/sites/11/2018/05/moores-law-electronics.pdf https://newsroom.intel.com/wp-content/uploads/sites/11/2018/... [2] http://www.monolithic3d.com/blog/is-there-a-fundamental-limit-to-miniaturizing-cmos-transistors1 http://www.monolithic3d.com/blog/is-there-a-fundamental-limi...

by tomxor 6y ago

CyberDildonics 6y ago

Moore's law is about transistor count. Not only that but you are saying the exact opposite in reply to someone else, claiming that process node sizes don't matter.

tomxor 6y ago
Moores law is about the rate of transistor count AND the implications. If you read Moore's paper you will find the context in which the definition resides is based on transistor scale, and the implication was even explicitly expressed in the very same paper by Moore - He observed that transistor doubling by reduced transistor scale gave faster clock at the same power density for the same die area. This is no longer true, we are barely still reducing transistor scale (but no longer uniformly), and no longer gain any of the other benefits due to the break down of Dennard scaling, coincidentally at the same time it became difficult to continue to reduce transistor channel scale.
- CyberDildonics 6y ago
  > rate of transistor count That doesn't really make sense. It was actually about transistor count and cost. > faster clock at the same power density That's Dennard scaling as someone already mentioned to you You said: > Transistor scaling (dennard scaling) Those are two different things. You also said: > We haven't been making significant progress over the last decade in terms of process size, This is false by any reasonable definition, since as has already been said by multiple people, transistors are a fraction of the size they were ten years ago and the density has gone up considerably. > coincidentally at the same time it became difficult to continue to reduce transistor channel scale. Frequencies did not go up, but transistors shrunk, I'm not sure why you keep trying to state otherwise. How do you explain the enormous rise in transistor count and process shrinkage over the last decade? You are literally stating something that is false and not even backing up what you are saying with any information at all.
  - tomxor 6y ago
    I've no wish to be so adversarial with you, but there are clearly some misunderstandings between us so I'll try to answer your questions. but then I'm done. As I have already admitted in the sibling thread, it is not as simple as transistor scaling stopping outright, I was clearly _wrong_ to suggest that... but it's also untrue to suggest transistor scaling has not stopped in any way - this is essentially the point I am still trying to make for you: Features are getting stuck due to various fundamental limits, and we no longer get the same benefits as a result, and this all started at the same time we stopped getting significant speed improvements (the breakdown of Dennard scaling). >> rate of transistor count > That doesn't really make sense. It was actually about transistor count and cost. Yes, but that is a bi-product, It is fundamentally about the exponential growth rate of transistor count per unit area which is only achieved sustainably (until fundamental limits) via transistor scaling. When that scaling is uniform we get not only reduced cost per transistor and but higher speeds: > Moore's law is the observation that the number of transistors in a dense integrated circuit (IC) doubles about every two years. [0] -- >> faster clock at the same power density > That's Dennard scaling as someone already mentioned to you Dennard scaling is a formalization of what Moore already observed in the very same paper a decade prior on page 3 under "Heat problem": > shrinking dimensions on an inte-grated structure makes it possible to operate the structure at higher speed for the same power per unit area. [1] This is the context of Moore's law, the only mechanism at the time that he was alluding to, uniform transistor scaling with all the benefits (including what is known as Dennard scaling today). This context is commonly lost by people who quote it today. -- > You said: >> Transistor scaling (dennard scaling) > Those are two different things. Yes they are, as I already admitted in the sibling subthread, I was technically incorrect to mix them, never the less they are closely related - Dennard scaling has always been related to transistor scale, and broke down at the same time uniform transistor scaling aka "classic transistor scaling" stopped. -- > You also said: >> We haven't been making significant progress over the last decade in terms of process size, > This is false by any reasonable definition, since as has already been said by multiple people, transistors are a fraction of the size they were ten years ago and the density has gone up considerably. I've already admitted this is inaccurate in the sibling thread. You can read my response there. However progress has been stifled to say the least. -- >> coincidentally at the same time it became difficult to continue to reduce transistor channel scale. > Frequencies did not go up, but transistors shrunk, I'm not sure why you keep trying to state otherwise. How do you explain the enormous rise in transistor count and process shrinkage over the last decade? You are literally stating something that is false and not even backing up what you are saying with any information at all. I am not disputing transistors have shrunk, but not all features of transistors have shrunk at the same rate, I'll add emphasis: channel lengths have become more difficult to reduce in scale. Here's a random source I found: > when we approach the direct source-drain tunneling limit, we could move to recessed channel devices and use channel lengths longer than the minimum feature size. This could allow us to continue miniaturization and increase component density. [2] i.e channel lengths will _not_ be 5nm Densities continue to increase while transistors can no longer be uniformly shrunk, in the same way a square can be made into a rectangle and have a smaller area while not reducing the maximum edge length. However it's intuitive to see that while this will continue to increase density, it will not necessarily increase speed - and it will not be long until we hit limits on scaling the other features. [0] https://en.wikipedia.org/wiki/Moore%27s_law https://en.wikipedia.org/wiki/Moore%27s_law [1] https://newsroom.intel.com/wp-content/uploads/sites/11/2018/05/moores-law-electronics.pdf https://newsroom.intel.com/wp-content/uploads/sites/11/2018/... [2] http://www.monolithic3d.com/blog/is-there-a-fundamental-limit-to-miniaturizing-cmos-transistors1 http://www.monolithic3d.com/blog/is-there-a-fundamental-limi...