In my field (FPGAs) master/slave is used correctly fairly often - having one module command another module is really common in HDL design. Although I'm happy to

In my field (FPGAs) master/slave is used correctly fairly often - having one module command another module is really common in HDL design. Although I'm happy to see "master/slave" gone, I haven't yet seen a good widely-adopted alternative. For example, "primary/secondary" is slowly being adopted, but I find it very confusing because it can also mean two modules that perform the same function in parallel, but have a different priority for receiving input.