You can have the CPU share the die with the secure cores, but you'd need to figure out a lot of complexity, like dealing with memory access pattern leakage due

You can have the CPU share the die with the secure cores, but you'd need to figure out a lot of complexity, like dealing with memory access pattern leakage due to a shared memory bus. The less things you share, the less the performant parts need to care about security, and the secure parts need to care about performance.