I also performed analysis of this algorithm as part of a work engagement, and came to similar conclusions to you (that it's not nearly as ASIC resistent as the

I also performed analysis of this algorithm as part of a work engagement, and came to similar conclusions to you (that it's not nearly as ASIC resistent as the authors claim). Notably there was (and still somewhat is, but less so [1]) very low data dependency between the generated instructions, which enables ahead-of-time preprocessing on a CPU to get effective execution on a bunch of independent compute units / datapaths (on an FPGA/ASIC), saturating all of them during a significant amount of time. [1] - https://github.com/tevador/RandomX/pull/118 https://github.com/tevador/RandomX/pull/118