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I would expect the problems to become both exponentially harder and exponentially more to solve as we scale down. But vice versa, using the process and knowledg
by threatripper 6y ago
I would expect the problems to become both exponentially harder and exponentially more to solve as we scale down. But vice versa, using the process and knowledge we gain from 5 nm chips might improve the lifetime of 7 nm chips by orders of magnitude. And again using the 4/3/2 nm process knowledge we might obtain very durable 5 nm chips in a few years.
- Causality1 6y agoIs there much of a market for medium-detail processes? We have the desktop/server/workstation/smartphone market using the very smallest detail processes, with maybe some categories using the previous-generation node. Then we have the embedded market which is everything from cheap-as-dirt 350nm microcontrollers to 28nm ARM chips. Nobody really wants the five-years-ago chips, the currently 18-22nm node. They're too expensive to buy by the million and not shiny enough to compete against the newest stuff.
- ksec 6y agoThere are plenty of market for in between 28nm to 12nm node. It is simply a natural progression between Cost, Features, Performance and Economics of Chips. Especially when they are the last few nodes before you move up to EUV. A10 / T2 used in many of the Apple Appliance are 16nm, along with dozens of WiFi, Modem, Ethernet Controller, ASIC / FPGA etc. These are easily 100M unit a year. As long as the cost benefits fits their volume they will move to next node.
- hwillis 6y agoASICs?
- hwillis 6y ago> But vice versa, using the process and knowledge we gain from 5 nm chips might improve the lifetime of 7 nm chips by orders of magnitude Probably not. The problems at each scale are very different and tend not to have much overlap. Process limitations also exist regardless- say you figure out that patterning transistors at 3 nm increases lifetime in a way that is applicable to 7 nm. 7 nm still can't take advantage of it as long as it requires 3 nm scale patterning, if there is even overlapping technology. Even if it requires adding a new step, say a wafer treatment that is necessary at 3 nm but optional at 7 nm, the economic benefit from increased lifespan is probably not worth retooling the old equipment.