Mine too at UIUC almost 20 years ago! We had to design a working CPU for the instruction set in verilog or VHDL, then run a program in the simulator. I still v

Mine too at UIUC almost 20 years ago! We had to design a working CPU for the instruction set in verilog or VHDL, then run a program in the simulator. I still vaguely remember that exactly one instruction needed 2 passes through the core pipeline. During decode, we would inject the reserved word into the instruction pipeline to represent the 2nd pass. We were pretty proud of that "innovation".