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Some processors implement "Instruction Level Parallelism" where you can do arithmetic on many values simultaneously with special assembly instructions. The mos
by neutronicus 6y ago
Some processors implement "Instruction Level Parallelism" where you can do arithmetic on many values simultaneously with special assembly instructions.
The most widespread cases of this (SSE, AVX2) came from Intel trying to get lock-in in the high-performance computing market. So it took a while for AMD to sell chips that implemented these instructions and even Intel's catalog doesn't uniformly offer them.
It's also tough to get the compiler to emit these instructions where you want even if it knows they're available (unsurprisingly, since you're asking it to auto parallelize a computation), so in the high-performance space a lot of people just have to resort to inline assembly.
- masklinn 6y agoThis sort of instructions you often have intrinsics for though.
- neutronicus 6y agoAh, yeah, in my head I tend to conflate intrinsics and inline assembly
- jlokier 6y agoJust a minor terminology point. Instruction Level Parallelism (ILP) means something else. What you are describing, with special instructions, is called Single Instruction Multiple Data (SIMD), or simply vector instructions. ILP means the execution of multiple separate instructions in parallel per clock cycle, though techniques like superscalar, out-of-order and speculative execution. ILP is sometimes used as a measure: How many instructions per cycle can be issued. It does not require special instructions, it's just the hardware being clever about running existing instructions faster.
- neutronicus 6y agoAh, we used that wrong in my old group then. We talked about Instruction Level Parallelism vs. Thread Level Parallelism vs. Node Level Parallelism since generally if you are working on a problem with some data dependency you will really have to think about each separately to get the best performance.