3 ms·
> using processor features that aren't exposed by the kernel or standard library). As someone who doesn't do any low-level work, could you give an example of t
by gizmo385 6y ago
> using processor features that aren't exposed by the kernel or standard library).
As someone who doesn't do any low-level work, could you give an example of these kinds of features? I'd like to read into some of them :)
- fluffything 6y agoJust take any operating systems course and try to implement your own. Or try to program a micro-controler "hello world" that actuates an LED ?
- masklinn 6y agoAren't those usually MMIO?
- AndrewGaspar 6y agoI used inline assembly once when playing around with Rust on GPUs to get Cuda's implicit thread ID and grid ID: https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#identifiers https://docs.nvidia.com/cuda/parallel-thread-execution/index...
- neutronicus 6y agoSome processors implement "Instruction Level Parallelism" where you can do arithmetic on many values simultaneously with special assembly instructions. The most widespread cases of this (SSE, AVX2) came from Intel trying to get lock-in in the high-performance computing market. So it took a while for AMD to sell chips that implemented these instructions and even Intel's catalog doesn't uniformly offer them. It's also tough to get the compiler to emit these instructions where you want even if it knows they're available (unsurprisingly, since you're asking it to auto parallelize a computation), so in the high-performance space a lot of people just have to resort to inline assembly.
- masklinn 6y agoThis sort of instructions you often have intrinsics for though.
- neutronicus 6y agoAh, yeah, in my head I tend to conflate intrinsics and inline assembly
- jlokier 6y agoJust a minor terminology point. Instruction Level Parallelism (ILP) means something else. What you are describing, with special instructions, is called Single Instruction Multiple Data (SIMD), or simply vector instructions. ILP means the execution of multiple separate instructions in parallel per clock cycle, though techniques like superscalar, out-of-order and speculative execution. ILP is sometimes used as a measure: How many instructions per cycle can be issued. It does not require special instructions, it's just the hardware being clever about running existing instructions faster.
- neutronicus 6y agoAh, we used that wrong in my old group then. We talked about Instruction Level Parallelism vs. Thread Level Parallelism vs. Node Level Parallelism since generally if you are working on a problem with some data dependency you will really have to think about each separately to get the best performance.
- woodruffw 6y agoMy go-to example of this is CPU-level virtualization support, like AMD-V or VT-x. Some C/C++ compilers will expose these instructions as intrinsics, but AFAIK Rust doesn't.
- JoshTriplett 6y agoMoving into or out of a control register, such as to enable a processor feature. Disabling or enabling interrupts. Reading or writing model-specific registers. Saving registers, switching stacks, and calling another function, then switching back and restoring registers when the function returns. Initializing and using hardware virtualization features (e.g. Intel VT). Using features like SMAP (preventing accidental access from the kernel to user memory through a wild pointer, temporary enabling it in careful dedicated routines like copy_from_user and copy_to_user). Making raw system calls from userspace.