3 ms·
No surprise that it's got a large L1 instruction cache given that it's a VLIW. Those aren't known for small code sizes, though I wonder why we don't tend to se
by Symmetry 6y ago
No surprise that it's got a large L1 instruction cache given that it's a VLIW. Those aren't known for small code sizes, though I wonder why we don't tend to see variable length VLIW architectures?