Re: ISR priorities. I agree with you somewhat. Technology is always changing. Many architectures don't have a rich interrupt controller. A system built to t

Re: ISR priorities. I agree with you somewhat. Technology is always changing. Many architectures don't have a rich interrupt controller. A system built to take advantage of the Cortex-M NVIC will have different characteristics than one that doesn't. For those who are unaware, the NVIC effectively turns the interrupt handling system into a hardware-based FIFO strict realtime task scheduler. The only hard limit is that since all of the tasks are executed on the same stack frame that you need an interrupt stack large enough for the maximum nesting depth. You can safely do much more work in an interrupt handler with such a system than you can in a classical non-nested interrupt-handling system.