4 ms·
I don't think that's necessarily true. I've worked with a couple of cacheful CPUs that only used parity checks on caches, not ECC. To get safety, the cache ha
by brandmeyer 6y ago
I don't think that's necessarily true. I've worked with a couple of cacheful CPUs that only used parity checks on caches, not ECC. To get safety, the cache has to be set up as write-through instead of write-back, so that it is almost always safe to throw away a line that suffers a parity error.
- vardump 6y agoAt least I've seen Machine Check Exceptions on x86 CPUs about L3 ECC errors on non-Xeon CPUs. I'd presume also other levels are protected.