3 ms·
I’m now curious about their memory structure, are they just using off the shelf multibit ECC memory?
by skunkworker 6y ago
I’m now curious about their memory structure, are they just using off the shelf multibit ECC memory?
- vardump 6y agoYou might need multibit ECC also in CPU caches. Pretty much all CPU caches have ECC, but no idea how large of an error they can fix. Then again, probably control logic is running on something radiation hardened and GUI layer (with some redundant hardware) can be easily rebooted as necessary.
- brandmeyer 6y agoI don't think that's necessarily true. I've worked with a couple of cacheful CPUs that only used parity checks on caches, not ECC. To get safety, the cache has to be set up as write-through instead of write-back, so that it is almost always safe to throw away a line that suffers a parity error.
- vardump 6y agoAt least I've seen Machine Check Exceptions on x86 CPUs about L3 ECC errors on non-Xeon CPUs. I'd presume also other levels are protected.