Modern chips are full of "logically blank" spots. That is, chips are often sold with 2 cores enabled when they physically contain 4 cores, sold with certain par

Modern chips are full of "logically blank" spots. That is, chips are often sold with 2 cores enabled when they physically contain 4 cores, sold with certain parts of the ISA disabled (AVX) even though the execution units are present, sold with less cache than physically present, etc. Sometimes this is a necessary result of binning (e.g., those cache slices didn't work), but mostly it is a result of pricing strategy: you want to charge more to the customers who are willing to pay more, while still capturing those who will pay less. Building chips is expensive, but not that expensive on a unit basis, so whether you sell a die for $100 or $20,000 you are still making a (marginal) profit. Given that context, it's not surprising that chips can also have actually blank spots which are not enabled on any chip: in this case because the SKX and SKL designs are tightly bound, so the floorplan is almost the same for both chips. This is probably either as a result of co-design, where SKL was designed with the future SKX in mind, meaning that SKX needed minimal changes to the core port over SKL, or as a result in a change of strategy: perhaps most SKL parts were originally slated to have AVX-512, on 10nm, but when 10nm was repeatedly delayed, the power or other impact was too high for most of the 14nm line and so AVX-512 was relegated to the SKX family. Who knows. What is clear is that SKL was definitely laid out with AVX-512 in mind.