4 ms·
What I want to know is what, if any, are the implications for CPU architecture. How should bignum arithmetic be efficiently implemented in hardware?
by gautamcgoel 6y ago
What I want to know is what, if any, are the implications for CPU architecture. How should bignum arithmetic be efficiently implemented in hardware?
- not2b 6y agoSince good bignum libraries already use tricks like this, and many others besides (like using FFT to handle very large bignum multiplication), it doesn't seem that the hardware needs to change.
- kwillets 6y agoThere's a whole subfield of adder design focused on carrying, since it's a big dependency chain even within one register. I believe this is a software version of what some adder circuits already do (although I'll need some reading to check).