3 ms·
Of course, but he article author did build it on a specific system and said the boot speed, so saying that clock rate would have also been a useful data point i
by tasty_freeze 6y ago
Of course, but he article author did build it on a specific system and said the boot speed, so saying that clock rate would have also been a useful data point if the platform is known. Someone using a different FPGA could use rough scaling factor to guesstimate what they might achieve for the platform they have on hand.
- thalain 6y agoAdded this to the article - it's 100 MHz in this design. For some more performance info on Vex in general, see https://github.com/SpinalHDL/VexRiscv https://github.com/SpinalHDL/VexRiscv We've yet to make detailed analyses on the multicore version, but in general I'd say it's pretty decent.