RISC-V as an ISA is designed to be easy to implement. You can get a simple implementation in 3k lines of Verilog [1]. That being said, there's a huge differenc

RISC-V as an ISA is designed to be easy to implement. You can get a simple implementation in 3k lines of Verilog [1]. That being said, there's a huge difference between a toy / simple multi-cycle machine-mode RISC-V core and one with a modern, performent microarchitecture (pipelined, super-scalar, multi-issue, cache coherent across multiple cores, with efficient branch prediction). There's also extra work to implement RISC-V extensions that let you run any 'real' code like Linux (which requires anything from simple ISA extensions to implementing the Privileged Instruction spec which dictates additional things like the MMU and interrupt controller). [1] - https://github.com/cliffordwolf/picorv32/blob/master/picorv32.v https://github.com/cliffordwolf/picorv32/blob/master/picorv3...