4 ms·

Can programs be written such that they switch between AVX-512 for L1 and AVX-256 for L2/L3? The decision by the compiler to switch to AVX-256 due to AVX-512 dow

Can programs be written such that they switch between AVX-512 for L1 and AVX-256 for L2/L3? The decision by the compiler to switch to AVX-256 due to AVX-512 downclocking / throttling based on a processor flag seems biased towards bursting / low voltage mode and fragile. But, an alternative of having JIT instructions emitted based on the current voltage profile seems of questionable benefit. Does 2nd store port only work with / benefit L2 or also L3?

BeeOnRope 6y ago
You can't write a program that does that automatically, but if you had a "cache aware" program that knows what writes are likely to hit in what level of the cache, you do it at the software level. I have my doubts it would be worth it though and it sounds difficult and fragile. I'm not sure what you mean by the 512 downlock: nothing I describe in the article has much to do with a downclock, except for the L1 effect at the beginning, and this was honestly fairly specific to the original test structure, which alternated periods of spinning on a timer with running a short test interval. It wasn't actually a downclock either (this CPU does not downclock for AVX-512 at 3.5 GHz: it has very little downclocking at all): rather it's dispatch throttling: the CPU still runs at full speed, but instructions are prevented from dispatching every cycle, effectively slowing the throughput, until the voltage can adjust to the heavier instructions. "Store ports" are only a concept that apply to the core itself, not the caches. Ports are entry points for execution of a certain type of instruction. Older CPUs had one store port (p4) and Ice Lake has two (p4 and p9), so two stores can execute in a single cycle. So these ports only benefit the core and don't interact with the L2 or L3 directly, which operate on a cache line basis. Caches also have something called ports, e.g., a cache might have 2 read and 1 write ports, meaning 2 reads and 1 write per cycle, but there isn't any indication these have changed in Ice Lake.

BeeOnRope 6y ago

You can't write a program that does that automatically, but if you had a "cache aware" program that knows what writes are likely to hit in what level of the cache, you do it at the software level. I have my doubts it would be worth it though and it sounds difficult and fragile. I'm not sure what you mean by the 512 downlock: nothing I describe in the article has much to do with a downclock, except for the L1 effect at the beginning, and this was honestly fairly specific to the original test structure, which alternated periods of spinning on a timer with running a short test interval. It wasn't actually a downclock either (this CPU does not downclock for AVX-512 at 3.5 GHz: it has very little downclocking at all): rather it's dispatch throttling: the CPU still runs at full speed, but instructions are prevented from dispatching every cycle, effectively slowing the throughput, until the voltage can adjust to the heavier instructions. "Store ports" are only a concept that apply to the core itself, not the caches. Ports are entry points for execution of a certain type of instruction. Older CPUs had one store port (p4) and Ice Lake has two (p4 and p9), so two stores can execute in a single cycle. So these ports only benefit the core and don't interact with the L2 or L3 directly, which operate on a cache line basis. Caches also have something called ports, e.g., a cache might have 2 read and 1 write ports, meaning 2 reads and 1 write per cycle, but there isn't any indication these have changed in Ice Lake.