3 ms·
I would always say that the important thing is the paradigm you need to adopt when writing RTL. Whether it's VHDL or systemverilog, the differences are details.
by Traster 6y ago
I would always say that the important thing is the paradigm you need to adopt when writing RTL. Whether it's VHDL or systemverilog, the differences are details. It's like programming C# vs Java, they have the same core concepts. But if you hand a C# Developer VHDL/SystemVerilog/Prolog they're not going to have a good time.
- tails4e 6y agoThat's a good point,the dataflow can be confusing to understand at first, especially when used to a purely procedural paradigm. In a way its similar to the differences between functional and imperative programming, and you first need the right mindset/basis for how it works before you can be productive. Once you understand the concurrent nature being described by HDLs, it begins to make sense - I always elaborate my HDL (actually usually other folks code) so I can see the dataflow that's being inferred graphically and it's very useful