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This seems to be using some sort of homegrown python system (migen) for fpga development. If you really want to learn fpga/asic development do yourself a favor
by panpanna 6y ago
This seems to be using some sort of homegrown python system (migen) for fpga development.
If you really want to learn fpga/asic development do yourself a favor and learn a real hardware description language such as verilog or vhdl. It is really not that hard. If you have some minimal knowledge in digital systems you will be up and running in a few hours.
And with a good teacher it will be really fun:
https://www.fpga4fun.com/ https://www.fpga4fun.com/
- tails4e 6y agoI Fully agree. Learning Verilog, or ideally SystemVerilog, to a basic level is important to have as a foundation for when you may need to build more advanced designs. I'm in favour of more high level languages being developed for HW generation, but I've yet to see a true replacement language for the main HDLs. For a counter and blinking led example, Verilog is very easy to read/understand for a beginner.
- Traster 6y agoI would always say that the important thing is the paradigm you need to adopt when writing RTL. Whether it's VHDL or systemverilog, the differences are details. It's like programming C# vs Java, they have the same core concepts. But if you hand a C# Developer VHDL/SystemVerilog/Prolog they're not going to have a good time.
- tails4e 6y agoThat's a good point,the dataflow can be confusing to understand at first, especially when used to a purely procedural paradigm. In a way its similar to the differences between functional and imperative programming, and you first need the right mindset/basis for how it works before you can be productive. Once you understand the concurrent nature being described by HDLs, it begins to make sense - I always elaborate my HDL (actually usually other folks code) so I can see the dataflow that's being inferred graphically and it's very useful
- colejohnson66 6y agoIt was my understanding that Migen “compiled” down to an actual HDL that’s then synthesized? Or was that not the case?
- panpanna 6y agoI don't know about migen, but this is generally how these tools work.
- krupan 6y agoThe slides start with VHDL, and then transition to Migen which is a well-known open source project that has been around for quite a while. A "homegrown" tool would be more like: the many bash/tcl/perl/python scripts that every professional chip design team in the world hacks together and never fully maintains or releases as open source.
- panpanna 6y agoI don't know your relation to migen but to me it was completely new. There are a large number of similar tools available, with MyHDL being the most popular one and Chisel the most hyped for now. They all have the same idea: instead of learning digital design you can use your sw development skills (while using this extremely awkward syntax) to design hardware. None work well enough to be used outside some niche area. Intel and AMD are using systemverilog and don't plan to change it. Even chisels posterchild RISC-V was eventually ported to pure verilog and that's what most people are using now.
- krupan 6y ago"instead of learning digital design you can use your sw development skills" That is not a claim I've heard from any of these tools. They are all still billed as hardware description languages, just better HDLs than (System)Verilog or VHDL, which is certainly arguable. What you are referring to with that statement is the snake oil that EDA vendors call High Level Synthesis (HLS). "Just write your algorithm in C and our tool will turn it into gates!"