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The Linux Kernel FPGA Subsystem
- baybal2 6y agoSince when it was in the kernel?
- Znafon 6y agoThe first commit is from Oct 7 2015.
- mhh__ 6y agoWhat kind of data throughout can you get with this? I've always wanted to play with something like this but FPGAs worth connecting to a PC are $$$.
- wyldfire 6y agoThroughput? Programming throughput or I/O? You should be able to saturate the bus. It's all dependent on what kind of processing takes place on either end. AWS offers FPGAs for rent [1] starting at around 1.50 USD/hr -- perfect if you want to dip your toes in without a huge capital expense. [1] https://aws.amazon.com/ec2/instance-types/f1/ https://aws.amazon.com/ec2/instance-types/f1/
- btashton 6y agoYou can find some shitcoin mining flops that are $300-$400 worth of hardware being sold off for $60 that are PCIe cards. There are a few examples in the LiteX project.
- gravypod 6y agoDo you have any links? I'd love to get my hands on some PCIe FPGAs and start messing with them
- aswanson 6y agoArtix-7 xilinx fpgas have a pcie interface and are lower priced.
- btashton 6y agoThis is what I am currently working on. I think I paid $80 to get one shipped to the US most of them seem to be in eBay in Europe. https://twitter.com/enjoy_digital/status/1257985111469015040 https://twitter.com/enjoy_digital/status/1257985111469015040
- myself248 6y agoThere are all sorts of old FPGA-in-a-PCI-slot dev boards floating around eBay, with a few nice looking ones under $300 if that's attractive.
- RL_Quine 6y agoWay cheaper. I have some Kintex7 PCI boards that were under $150 from aliexpress. Which is less than the cost of the FPGA.
- anfractuosity 6y agoNeat that looks pretty cool, I assume Kintex7 doesn't work in Vivado webpack though? Edit: Or at least the K420T board I found doesn't seem to be supported: https://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html#architecture https://www.xilinx.com/products/design-tools/vivado/vivado-w...
- non-entity 6y agoAdmittedly, I'm pretty ignorant of FPGA's right now, but I was curious about PCIe based boards a while back and was able to find some moderately priced ones such as https://www.latticesemi.com/products/developmentboardsandkits/ecp5pciexpressdevkit https://www.latticesemi.com/products/developmentboardsandkit... It's around $300, which might not be cheap, but it's certainly more affordable than other I've seen which are very much out of the range of any hobbyists.
- 5- 6y agothat one has been superseded by the ecp5 versa. https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5VersaDevelopmentKit https://www.latticesemi.com/en/Products/DevelopmentBoardsAnd... it's still $275, and in addition to lattice tools, it is well supported by the open source trellis/yosys/nextpnr flow: https://github.com/SymbiFlow/prjtrellis https://github.com/SymbiFlow/prjtrellis
- jsjohnst 6y ago> FPGAs worth connecting to a PC are $$$ I guess it depends on your own definition of worth and what’s worthy of a $$$ signifier of expense, but you can get pretty powerful FPGAs for $100-200 these days, and respectable ones that can serve many use cases for under $100.
- yummypaint 6y agoCame across a pretty clear video with an iCE40 and a rasPI showing the concept, though its from 2017. Presumably it would be a similar process to do this with a pci card? https://www.youtube.com/watch?v=nIEB1VAGUcs https://www.youtube.com/watch?v=nIEB1VAGUcs
- elevation 6y agoThis subsystem will configure an FPGA attached to your host by sending it a bitstream you provide. You still have to use your FPGAs vendor tools to generate the bitstream. One popular use case is for System-on-Chip (SoC) designs that pair a Processor System (PS) with Programmable Logic (PL); once the PS is running the kernel, the FPGA Manager can be used to program the PL fabric from kernel space. FPGA Manager has another handy feature for FPGA images that implement new peripherals on buses like SPI, I2C, PCI, AXI, etc. These devices are not "discoverable" in the sense that they are capable of communicating to the kernel what driver must be loaded to support them. So in along with a bitstream, FPGA Manager accepts a device tree overlay which indicates to the kernel what drivers to load for the new resources implemented by the configured FPGA. This causes the kernel to probe the requisite drivers after the FPGA configuration has completed. The FPGA manager can also unload drivers for devices implemented in an FPGA that is being reconfigured. Unfortunately, in LTS kernels 4.9 and 4.14, while SoC vendors include support for their own PL targets, the FPGA Manager subsystem was written as a singleton; once you've configured e.g, the PL, you can't configure additional peripheral FPGAs.
- qubex 6y ago> was written as a singleton Can you please explain this? What does it mean exactly? And is it different in versions of the kernel that aren’t the ones you explicitly mention?
- ouzu 6y agoA singleton is a design pattern making sure only one instance of an object can exist
- qubex 6y agoI know the term but I can’t quite understand how to interpret it in this specific context. Does it mean you can only program an FPGA once? Only one FPGA? One object per bus? I really don’t understand it.
- 6y ago
- bawana 6y agoIs there a tutorial for dummies somewhere? I want to implement my deep learning model in an fpga to see if it would be faster.
- czig 6y agoI like this book: https://github.com/hamsternz/IntroToSpartanFPGABook/blob/master/IntroToSpartanFPGABook.pdf https://github.com/hamsternz/IntroToSpartanFPGABook/blob/mas... It’s free and the exercises are very helpful for getting some hands on experience.